A computer can be thought of as a bit-stream transportation system wherein groupings of binary digits are moved from place to place, undergoing the various changes necessary for a particular application. Computers and microprocessor based systems generally include a data source which generates the data to be transferred, such as an address counter and a data memory which outputs data, and data receivers or "acceptors" such as output displays, printers, encoders, numerical control devices, and the like which receive the data from the source and operate accordingly. Data transfer systems coordinate such data movement from the source to the acceptors.
Within the computer, and even within the microprocessor itself, there is a multipartite bus structure serving as a data transfer system. Data can be moved serially (bitwise) or in parallel (bytewise). Bitwise transfer proceeds one bit at a time sequentially on a single wire. Bytewise transfer is the simultaneous parallel transfer of eight bits on eight wires.
One industry standard for parallel transfer is the Institute of Electrical and Electronics Engineers (IEEE) 488.1 standard also adopted by the American National Standards Institute (ANSI) and described in the patent to Ricci (U.S. Pat. No. 3,810,103; RE 29,246). The usual IEEE-488.1 system comprises a host computer and a daisy chain of devices each with some degree of "intelligence". Thus, with a single input/output port, a computer can host a full complement of peripherals: disk drives, printers, plotters, and laboratory instruments. To keep things organized, each device has its own "address" for each of its capabilities and responds accordingly when thus addressed. All of the devices can be addressed more or less simultaneously, the operations being handled by an interface manager in the IEEE 488.1 bus. The IEEE 488.1 bus consists of eight bidirectional data lines, five bus management lines, and three handshaking lines. The handshaking lines accept control signals that establish agreement between two components so that each can communicate with the other. In practical terms, the handshaking signals indicate that one component is ready to receive data while the other is ready to send data. The goal is to send data to the receivers only when they are ready to accept data and are not "busy" or otherwise incapable of receiving data. A corollary goal is to assure each receiver has accepted the data sent by the source.
Hence, the prior art handshake process includes the use of three control signals, by 5 convention termed "data-valid" (DAV), "ready for data" (RFD) and "data accepted" (DAC).
Also by convention, the source generates a low DAV signal when data on the lines is available, valid, and may be accepted by the receivers. The source generates a high DAV signal when data is removed or otherwise no longer valid.
The receivers generate a high RFD signal only when all the receivers are ready to accept data, and a low RFD signal when at least one receiver is not ready to accept data (i.e. one receiver is `busy`. The receivers also generate a high DAC signal when all data is accepted from the source, and a low DAC signal when all data has not yet been accepted from the source.
The prior art recognized that data receivers or acceptors such as output displays, printers, encoders, and the like generally have different response times to applied data signals and that such acceptors may also require different periods of operation before being ready again to respond to newly applied data signals. Because the prior art process is designed to facilitate multiple simultaneous acceptors or receivers, however, and wait as long as required for all the receivers to complete each handshake step, the low to high transitions of the RFD and DAC signals between each successive byte of information are accomplished with passive "pullup" circuitry. This allows any acceptor to keep these signals at a low voltage level with an active driver circuit, even if the other acceptors have enabled their passive pullup circuits. However, because passive pullups are used to drive the RFD and DAC signals high, the time for the low to high voltage transition is determined by RC time constant introduced by pullup resistance and the capacitance of the cable. The time required to achieve all the signal transitions is the major limiting factor in system speed.
Hence, the normal IEEE 488.1 basic data transfer rate is 0.25 megabytes/second. This rate may be increased to 1 or 1.5 megabytes/second by following certain cabling and electrical restrictions outlined in section 5.2 of the IEEE standard. Since, however, the three wire handshake sequence repeats for every data byte transfer, the key speed limiting steps are where the receiver handshake signals go from a low to a high logic level. The receivers drive the signals actively low, but allow the signals to go high by removing the active low drive and letting pullup resistors bring up the voltage. This method, called "wire-OR", requires the handshake RFD signal be driven low between each byte transferred and remain low until all the receivers are again ready for data transmission. After the transmission of one byte, RFD is allowed to be pulled high. Similarly, DAC is driven low when DAV is high and not allowed to go high until each receiver has completed accepting data. The time for the low to high voltage transmission on the RFD and DAC signals is determined by the number of devices in the system and the total cable length. The IEEE 488.1 specified cable has a significant capacitance that must be charged by the pullup resistors in the IEEE interfaces of the devices. In the best case, with short cables and very fast logic in the IEEE 488.1 interfaces, the three wire handshake (RFD, DAC, DAV) still limits the data transfer rate to around 1.5 megabytes/second. The IEEE 488.1 standard refers to a "nominal rate" of 1.0 megabytes/second which is the physical limit for a full system with 15 meters of cable.
Therefore, the IEEE 488.1 handshake process allows arbitrarily slow devices and multiple listeners operating at different speeds to delay successive data byte transfer but at the cost of limiting the maximum possible speed. Until now, this has been a "speed barrier," perceived as a fundamental part of IEEE 488.1 systems, much as the sound barrier was thought at one time to be an absolute limit to flight speed.
In some cases, the designers of such devices have provided auxiliary data output interfaces of a proprietary custom design to achieve higher speeds, but such interfaces suffer from the need to build custom hardware to interconnect these devices.